1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to an N-channel and a P-channel metal oxide semiconductor field effect transistor MOSFET.
2. Description of the Prior Art
N(P)-channel metal oxide semiconductor field effect transistors (MOSFETS) used in the dynamic random access memory (DRAM) technology must have very low OFF (standby) current to reduce the power consumption of the entire memory chip.
One of the ways to design a MOSFET with low OFF current is to use a high dose threshold voltage (V.sub.T) boron (arsenic) implant for the channel of the transistor. This high dose boron (arsenic) implant in the channel effectively increases the potential barrier between the channel and the drain and thereby decreases the standby current of the device with a gate to source voltage V.sub.GS =0 volts and the drain to source voltage V.sub.DS =2.5 or 3.6 volts depending on the voltage supply for the particular technology. However, a problem with the boron (arsenic) implant is substrate sensitivity due to the implant tail. Substrate sensitivity is defined as the rate of increase in threshold voltage, V.sub.T, due to the increase in source to substrate voltage, V.sub.SX. In other words, substrate sensitivity=.tangle-solidup.V.sub.T /.tangle-solidup.V.sub.SX. High substrate sensitivity is a very undesirable feature for any CMOS technology, because this element decreases the current drive capability of an N(P)-channel MOSFET.